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Meet the Team
Cisco Silicon One (#CiscoSiliconOne) brings together networking, compute and storage all in a single system. Come join us and take part in shaping Cisco’s revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, Security etc.). Our Hardware and Software solutions are tightly coupled with the development cycles that give us an unparalleled advantage in enabling our customers adopt the latest what technology can offer. As part of Cisco Silicon One (#CiscoSiliconOne) our team develops complex, high-performance, feature-rich ASICs used in Cisco's networking products and third-party custom-built hardware solutions.
Your Impact
You will be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL Design.
Key responsibilities:Create micro-architecture specifications and participate in reviewsImplement Verilog RTL to meet timing and performance requirements.Help define, evolve, and support our design methodology.Collaborate with the verification team on as-needed basis to address design bugs and close code coverage.Work closely with physical design team to close design timing and place-and-route issuesTriage, debug, and root cause simulation, software bring-up, and customer failures.Perform diagnostic and post silicon validation tests in the lab.Minimum Qualifications:Bachelor's in Electrical or Computer Engineering and 12+ years of related work experience or a Master’s Degree in Electrical or Computer Engineering and 8+ years of related work experience.Prior experience with developing Micro-Architecture for blocks.Prior experience with Verilog/System Verilog.Prior experience with Clock Domain, Reset Domain Crossing issues, and Low-Power Design Techniques.Prior experience with simulators and waveform debugging tools.Prior experience working with Linting, Synthesis and Static Timing Analysis tools.Prior experience with Verification methodologies including experience developing testbenches, writing System Verilog Assertions and debugging Netlist simulations.Preferred Qualifications:Experience with Networking technologies and concepts.,Experience with ARM protocols (AXI, CHI, APB. AHB) and exposure to ARM CPU’s is desirable.Design experience with Ethernet MAC, DDR/LPDDR, PCIE and DMA controllers is a plus.Experience with Integrating 3rd party IP’s into SoC is desirableScripting experience (Python, Perl, TCL, shell programming) highly desirable.Experience with Emulation and Formal Verification tools is a plus.We Are Cisco
#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.
Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.
We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do!
Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!